As is known, many electronic devices can have their architecture re-configured, during manufacturing, by programming non-erasable memory cells, also known as CAM cells.
For example, some types of non-volatile memories (EPROMs, EEPROMs, Flash, etc.) allow replacement of defective lines or columns of a memory array by others, that are so called "redundant," to restore full functioning of the memory array. In this case, data concerning the presence of defective lines or columns and their position is stored in the aforementioned CAM cells, which are read in a power-up step of the memory, i.e., in the step in which the power is switched on.
CAM cells are generally organized in an array and are read using a reading device of the type shown in FIG. 1.
In FIG. 1, the reading device 1 comprises a plurality of cell read circuits 2, to read respective data cells 4, a read detection circuit 8 for detecting reading of the data cells 4, and a control circuit 10 for controlling cell read circuits 2 and read detection circuit 8.
Each cell read circuit 2, which is called hereinafter BCAM circuit 2, has a first input terminal 2a receiving a POR (Power On Reset) initialization signal supplied to output 6o by a generator circuit 6 (which is not part of the reading device 1 and is therefore not described in detail), with the purpose of detecting activation of the supply of reading device 1, or a loud noise on the supply line (a so-called "bump"). BCAM circuit 2 also has a second input terminal 2b connected to control circuit 10, and an output terminal 2o supplying, at the reading step, the data contained in the respective data cell 4.
Read detection circuit 8 has a first input terminal 8a connected to output terminal 6o of generator circuit 6, a second and a third input terminal 8b, 8c connected to control circuit 10, and an output terminal 8o which supplies a deactivation signal DIS to control circuit 10.
Control circuit 10, which is not shown in detail, has a first input terminal 10a which is connected to output terminal 6o of generator circuit 6; a second input terminal 10b connected to output terminal 8o of read detection circuit 8; a first output terminal 10o supplying a read activation signal UGV and connected to the second input terminal 8b of read detection circuit 8 and to data cells 4; and a second output terminal 10u supplying a read bias signal UC and connected to the third input terminal 8c of the read detection circuit 8 and to the second input terminal 2b of BCAM circuit 2.
Each data cell 4 preferably comprises a CAM cell that stores a binary datum (bit), the logic value of which (0 or 1) depends on whether the cell is written or virgin. Each data cell 4 has a drain terminal 4a, a source terminal 4b connected to ground, and a gate terminal 4c connected to the first output terminal 10o of control circuit 10, from which it receives read activation signal UGV.
Each BCAM circuit 2 comprises a data read bias circuit 16, a data storage circuit 18 and an initialization circuit 20, as well as programming bias circuits which are not shown.
Data read bias circuit 16 comprises an NMOS transistor having a drain terminal connected to a node LD1, a source terminal connected to the drain terminal 4a of the data cell 4, and a gate terminal connected to the second input terminal 2b of BCAM circuit 2.
Data storage circuit 18 comprises a first and a second inverter 22, 24 connected to one another back-to-back; in particular first inverter 22 is connected at its input to a node LD2 and at its output to a node LD1, and second inverter 24 is connected at its input to node LD1 and at its output to node LD2; node LD2 is also connected to output terminal 2o of BCAM circuit 2.
Initialization circuit 20 comprises an NMOS transistor having a drain terminal 20a connected to the node LD2, a source terminal 20b connected to ground, and a gate terminal 20c connected to the first input terminal 2a of BCAM circuit 2.
Read detection circuit 8 comprises a virgin, non-erasable reference cell 30, for example a dummy CAM cell, and a reference read cell 32 which is substantially identical to the above-described BCAM circuit 2, and is called hereinafter as dummy circuit 32.
In particular, dummy circuit 32 comprises a reference read bias circuit 34; a reference storage circuit 36 including two inverters 37 and 39 similar to inverters 22 and 24, and having an input node DLD1 and an output node DLD2; and an initialization circuit 38.
Dummy circuit 32 also includes a delay circuit 40, which for example comprises a plurality of inverters 42, and is connected between node DLD2 and output terminal 8o of read detection circuit 8.
Reading device 1 functions as follows.
As shown in FIG. 2, when power is switched on, generator circuit 6 generates a pulse which initializes the circuits of reading device 1; in particular initialization signal POR generated by the generator circuit switches to the high logic state, following initially the transient of supply voltage V.sub.DD. This pulse initializes data storage circuit 18 and reference storage circuit 36, switching on transistors 20 and 38 and causing the potential of output nodes LD2 and DLD2 to be close to ground (low logic state), and brings the potential of the input nodes LD1 and DLD1 to high level (high logic state). In the example illustrated, the high logic state of input node LD1 of data storage circuit 18 corresponds to a written data cell 4.
In this initialization step, read bias signal UC and deactivation signal DIS are in the low logic state, whereas read activation signal UGV, which is initially in the low logic state, has an edge that rises steeply to a high logic state that is substantially the same as that of the supply voltage V.sub.DD.
The initialization step of reading device 1 ends when initialization signal POR switches once again to low, giving rise to bias activation of data cell 4 and beginning of the step of reading data cell 4.
In particular, after initialization signal POR switches to low, control circuit 10 switches read bias signal UC to high, activating NMOS transistor 16, which then connects the drain terminal 4a of data cell 4 to input node LD1 of data storage circuit 18, thus biasing data cell 4.
The dimensions of the first inverter 22 are such that if data cell 4 is virgin, the current absorbed by the latter causes switching of node LD1 from the high logic state to the low logic state, whereas if data cell 4 is written, no switching of node LD1 takes place.
Simultaneously, substantially same events as those above described take place in read detection circuit 8, with the difference that since reference cell 30 is virgin, node DLD1 definitely switches, indicating that reference cell 30 has been read. This switching is propagated with a delay, via inverter 37 and delay circuit 40, to the output of read detection circuit 8, producing switching of deactivation signal DIS to the high logic state.
The object of introducing this delay is to ensure that all virgin data cells 4 are read, including those in which the read current required to switch node LD1 is reached more slowly, because of unintentional physical implementation differences or of a position making slower cell biasing. Consequently, switching of deactivation signal DIS shows with certainty that reading of all data cells 4 has taken place.
Deactivation signal DIS is switched by control circuit 10, which, if other functions are not activated, switches to the low logic state the read bias signal UC, which stops the read step of data cell 4, whereas read activation signal UGV remains high.
The sequence of the above-described events is determined by an "inherent" timing of reading device 1, i.e., by the duration of the initialization signal POR and the delay of the leading edge of deactivation signal DIS, compared with the leading edge of read bias signal UC.
This timing gives rise to the effects indicated, only if the initial transient on the supply line (rising ramp of supply voltage V.sub.DD) has a short duration with respect to the time constants associated with the internal nodes of reading device 1. On the other hand, if the initial transient on the supply line is lengthy, the events described take place whilst supply voltage V.sub.DD is still increasing towards the final value, and the sequence of events is no longer caused by the "inherent" timing of the reading device, but is dependent on a so-called "trigger voltage levels" of the circuits of reading device 1 (i.e., on a minimum supply voltage which, when supplied to a circuit, allows the latter to be switched, if it should be, from one logic state to the other).
If the initial transient on the supply line is lengthy, and the sequence of events depends on the so-called "trigger voltage levels" of the circuits, it is nevertheless possible to obtain the sequence of events illustrated in FIG. 2, if the following conditions have occurred:
zero trigger voltage of generator circuit 6 is lower than zero trigger voltage of read detection circuit 8; In particular, the term zero trigger voltage of generator circuit 6 indicates the minimum supply voltage which causes switching of generator circuit 6, thus producing the trailing edge of the initialization signal POR, whereas the term zero trigger voltage of read detection circuit 8 indicates the minimum supply voltage which, when signals UGV and UC have an equal value to the supply voltage V.sub.DD, enables reference cell 30 to take to the low logic state node DLD1 previously initialized to the high logic state, thus producing the leading edge of deactivation signal DIS; PA1 minimum read voltage of a virgin data cell 4 is lower than zero trigger voltage of read detection circuit 8, where the term minimum read voltage of a data cell 4 indicates the minimum supply voltage V.sub.DD which, when signals UGV and UC have an equal value to the supply voltage, gives rise to switching of node LD1 from high, to which it has previously been initialized, to low. This ensures that when the read step is completed, all virgin data cells 4 have actually been read.
The latter condition can be obtained by introducing in dimensional or structural differences into the components carrying out the same function in read detection circuit 8 and in BCAM circuits 2. For example, reference cell 30 can have a switching-on threshold voltage greater than data cells 4, or read activation signal UGV supplied to reference cell 30 can be lower than read activation signal UGV supplied to data cells 4. However both solutions have disadvantages, which are associated with the loss of correlation involved in variations of structural features of the data cells and the reference cell, and their deterioration in the long term.
The above-described reading device 1 has some disadvantages associated mainly with the timing of read bias signals UC and read activation signals UGV, and with the presence of steep leading edges of the signals.
In particular, the steep leading edge of read bias signals UC and read activation signals UGV gives rise to "fast" biasing of drain terminal 4a, and, respectively, of gate terminal 4c of data cells 4, which can be problematic if the supply lines are noisy, as is often the case in the power-up step, or when a somewhat high (6-7 V) supply voltage V.sub.DD is being used, since when they are switched to high, read bias signal UC and read activation signal UGV follow a behavior which coincides with the trend of supply voltage V.sub.DD.
In fact, an excessively high value of read activation signal UGV applied to the gate terminal 4c of a data cell 4 can be such that it leads to exceeding the conduction threshold voltage of the data cell 4, consequently generating a current which, although lower than that of a virgin data cell 4, can be sufficient to switch the data storage circuit 18 connected thereto, thus causing erroneous reading of the content of data cell 4, which cannot be corrected as long as power is on.
In addition, the high logic state of read activation signal UGV on gate terminal 4c of data cell 4, simultaneously with the initialization pulse, can cause conditions which are potentially dangerous for the data cell 4 in presence of undesirable electric fields, for example during electrostatic discharge on the integrated circuit pin connected to supply voltage V.sub.DD, thus reducing reliability of data cell 4.
Finally, immediate conduction of NMOS transistor 16, caused by the steep switching edge of read bias signal UC, gives rise to instantaneous connection between node LD1 and drain terminal 4a of data cell 4, and thus to an electric charge transfer from node LD1 (associated to an equivalent capacity charged to level 1) to drain terminal 4a (associated to an equivalent capacity charged to level zero). In case of fast activation of NMOS transistor 16, this charge transfer (also known as "charge sharing") can be sufficient to reduce significantly the voltage of node LD1, thus causing erroneous switching of data storage circuit 18 and of the voltage of node LD1 from the high logic state to the low logic state, with consequent erroneous reading of data cell 4.